1. Field of the Invention
The present invention relates to a demodulator with a phase-adjusting function, and in particular to a demodulator with a phase-adjusting function which is used for uniformly arranging two phases of an input modulated wave and a delayed modulated wave in a wave detecting section of the demodulator which demodulates a frequency-modulated wave.
2. Related Background Art
Whether a radio signal or a cable signal, in the signal processing field it is generally the case that when a frequency-modulated signal is demodulated in a digital demodulator, a demodulator must delay a base band signal by one cycle using a shift register comprising a flip-flop circuit (hereinafter, abbreviated as an FF circuit) inputted with a sampling clock as an input clock. Therefore, the demodulator requires an FF circuit having several hundred stages due to a signal to be delayed, and using a shift register comprising such an FF circuit with multiple stages results in an increase of the entire circuit scale of the demodulator.
In order to overcome the problem of increasing the demodulator circuit scale, it has been conventionally thought that the number of stages in the FF circuit should be reduced by frequency-dividing a sampling clock and by using the divided clock as a clock input for the FF circuit, but the following problems arise in the reduction of the number of the stages.
In case that the sampling clock is frequency-divided to produce a clock for the FF circuit, the cycle of the base band signal does not coincide with integer times the cycle of the clock for the FF circuit due to a frequency division ratio, and a phase of a clock for the FF circuit when a modulated wave with the original frequency and a delayed modulated wave are inputted in a multiplier causes “a phase shift” corresponding to a half cycle. There is a problem that such a “phase shift” causes lowering of a detection precision in the demodulator.
Further, adherence to maintaining the detection precision in the demodulator causes such a constraint that the cycle of a clock input into a delaying FF circuit must be multiplied by integer times the base band signal. Therefore, since a circuit for multiplication must be added newly, there occurs a problem that reduction in circuit scale of the entire demodulator is obstructed.